EACEN=EACEN_0, MRP=MRP_0, RRS=RRS_0, WRMFRZ=WRMFRZ_0
Control 2 Register
| EACEN | This bit controls the comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process 0 (EACEN_0): Rx Mailbox filter’s IDE bit is always compared and RTR is never compared despite mask bits. 1 (EACEN_1): Enables the comparison of both Rx Mailbox filter’s IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. |
| RRS | If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the corresponding Message Buffer in the same fashion of a Data Frame 0 (RRS_0): Remote Response Frame is generated 1 (RRS_1): Remote Request Frame is stored |
| MRP | If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching continues on the Rx FIFO 0 (MRP_0): Matching starts from Rx FIFO and continues on Mailboxes 1 (MRP_1): Matching starts from Mailboxes and continues on Rx FIFO |
| TASD | This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus |
| RFFN | This 4-bit field defines the number of Rx FIFO filters according to |
| WRMFRZ | Enable unrestricted write access to FlexCAN memory in Freeze mode 0 (WRMFRZ_0): Keep the write access restricted in some regions of FlexCAN memory 1 (WRMFRZ_1): Enable unrestricted write access to FlexCAN memory |